1. Field of the Invention
This invention relates to power-up control for integrated circuits and more particularly for power-up control for digital logic.
2. Description of the Related Art
At power up, while the power supply is ramping, the states of the sequential digital circuits, such as latches, registers, and flip-flops, may get stuck to some arbitrary logic levels. Thus, there is a need to force the latches, registers, and flip-flops into a known state using a reset signal. After the power supply reaches a known state by asserting the reset signal for a period of time, the sequential digital circuits enter a known state, and the reset is released. Many existing solutions use external resistor capacitor (R-C) components to achieve suitable delay to allow the reset signal to reset the digital logic, thus requiring additional dedicated pins to provide sufficient delay to ensure the sequential digital circuits have been reset with an appropriate power supply level. An on-chip R-C based delay circuit is not a practical solution due to the fact that the power supply may have a very slow ramp requiring a large on-chip silicon area to afford a sufficiently large R-C circuit. Accordingly, improvement in power-up control is desirable.